SATA FSL and upstreaming

[Zang Roy-R61911]

> -----Original Message-----
> From: Benjamin Herrenschmidt [mailto:benh at kernel.crashing.org]
> Sent: Thursday, May 16, 2013 2:54 PM
> To: Zang Roy-R61911
> Cc: Bhushan Bharat-R65777; tiejun.chen; Liu Qiang-B32616; Fleming Andy-
> AFLEMING; linuxppc-dev at lists.ozlabs.org; Xie Shaohui-B21989
> Subject: Re: SATA FSL and upstreaming
> 
> On Thu, 2013-05-16 at 06:49 +0000, Zang Roy-R61911 wrote:
> >
> 
> > Please also provide a RCW binary to Ben, if your guys insist updating
> the RCW.
> 
> right, I just noticed it's ascii :-) That isn't going to work well...
I just tried your RCW. one e1000 card works in slot7.
we may need to check others ...
U-Boot 2013.01-00078-g2741c99 (May 03 2013 - 00:20:41)

CPU0:  P5020E, Version: 2.0, (0x82280020)
Core:  E5500, Version: 1.2, (0x80240012)
Clock Configuration:
       CPU0:2000 MHz, CPU1:2000 MHz, 
       CCB:800  MHz,
       DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:100  MHz
       FMAN1: 600 MHz
       QMAN:  400 MHz
       PME:   400 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Reset Configuration Word (RCW):
       00000000: 0c540000 00000000 1e120000 00000000
       00000010: d8984a01 03002000 de800000 41000000
       00000020: 00000000 00000000 00000000 10070000
       00000030: 00000000 00000000 00000000 00000000
Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x02, FPGA Ver: 0x04, vBank: 4
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz 
I2C:   ready
SPI:   ready
DRAM:  Initializing....using SPD
Detected UDIMM i-DIMM
Detected UDIMM i-DIMM
2 GiB left unmapped
4 GiB (DDR3, 64-bit, CL=9, ECC on)
       DDR Controller Interleaving Mode: cache line
       DDR Chip-Select Interleaving Mode: CS0+CS1
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Remap DDR 2 GiB left unmapped

POST memory PASSED
Flash: 128 MiB
L2:    512 KB enabled
Corenet Platform Cache: 2048 KB enabled
SRIO1: disabled
SRIO2: disabled
NAND:  1024 MiB
MMC:  FSL_SDHC: 0
EEPROM: Invalid ID (ff ff ff ff)
PCIe1: Root Complex, x2, regs @ 0xfe200000
  01:00.0     - 8086:105e - Network controller
  01:00.1     - 8086:105e - Network controller
PCIe1: Bus 00 - 01
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe202000
PCIe3: Bus 02 - 02
PCIe4: disabled
In:    serial
Out:   serial
Err:   serial
Net:   Initializing Fman
Fman1: Uploading microcode version 106.1.6
PHY reset timed out
PHY reset timed out
PHY reset timed out
PHY reset timed out
e1000: 00:15:17:16:ce:b8
       e1000: 00:15:17:16:ce:b9
       FM1 at DTSEC1, FM1 at DTSEC2, FM1 at DTSEC3, FM1 at DTSEC4 [PRIME], FM1 at DTSEC5, FM1 at TGEC1, e1000#0
Warning: e1000#0 MAC addresses don't match:
Address in SROM is         00:15:17:16:ce:b8
Address in environment is  00:1b:21:68:5e:d4
, e1000#1
Warning: e1000#1 using MAC address from net device

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