SATA FSL and upstreaming

[tiejun.chen]

On 05/16/2013 02:09 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 06:05 +0000, Zang Roy-R61911 wrote:
>> I do not suggest changing the RCW. If the RCW is broken on Ben's side,
>> it is not easy to recover for him.
>> Let's check the U-boot output first.
>
> U-Boot 2013.01-00009-g7bcd7f4 (Mar 14 2013 - 14:23:16)
>
> CPU0:  P5020E, Version: 1.0, (0x82280010)
> Core:  E5500, Version: 1.0, (0x80240010)
> Clock Configuration:
>         CPU0:2000 MHz, CPU1:2000 MHz,
>         CCB:800  MHz,
>         DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:100  MHz
>         FMAN1: 600 MHz
>         QMAN:  400 MHz
>         PME:   400 MHz
> L1:    D-cache 32 kB enabled
>         I-cache 32 kB enabled
> Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 0
> Reset Configuration Word (RCW):
>         00000000: 0c540000 00000000 1e120000 00000000
>         00000010: d8984a01 03002000 de800000 41000000
>         00000020: 00000000 00000000 00000000 10070000
>         00000030: 00000000 00000000 00000000 00000000

I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then please take 
a look at this:

The RCW directories names for the p5020ds board conform to the following naming
convention:

ab_bcdefghi_j:

a = 'R' if RGMII at DTSEC4 is supported / 'N' if not available/not used
b = 'R' if RGMII at DTSEC5 is supported / 'N" if not available/not used

c = What is available in Slot 1 or SATA
d = What is available in Slot 2
e = What is available in Slot 3
f = What is available in Slot 4
g = What is available in Slot 5
h = What is available in Slot 6
i = What is available in Slot 7

For the Slots (c..i):
  'N' if not available/not used
  'P' if PCIe
  'X' if XAUI
  'R' if SRIO
  'S' if SGMII
  'H' if SATA
  'A' is AURORA

j = 'hex value of serdes protocol value'

So NR_HXAPNSP_0x36 means:
  - no RGMII at DTSEC4
  - RGMII at DTSEC5
  - SATA [Slot 1 not used]
  - XAUI on Slot 2
  - AURORA on Slot 3
  - PCIE on Slot 4
  - SGMII on Slot 6
  - PCIE on Slot 7

Slot 5 is not used, and the SERDES Protocol is 0x36.

So slot 7 and slot 4 can be as PCIe slot.

Tiejun

> SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz
> I2C:   ready
> SPI:   ready
> DRAM:  Initializing....using SPD
> Detected UDIMM i-DIMM
> Detected UDIMM i-DIMM
> 2 GiB left unmapped
> 4 GiB (DDR3, 64-bit, CL=9, ECC on)
>         DDR Controller Interleaving Mode: cache line
>         DDR Chip-Select Interleaving Mode: CS0+CS1
> Testing 0x00000000 - 0x7fffffff
> Testing 0x80000000 - 0xffffffff
> Remap DDR 2 GiB left unmapped
>
> POST memory PASSED
> Flash: 128 MiB
> L2:    512 KB enabled
> Corenet Platform Cache: 2048 KB enabled
> SRIO1: disabled
> SRIO2: disabled
> NAND:  1024 MiB
> MMC:  FSL_SDHC: 0
> EEPROM: NXID v1
> PCIe1: Root Complex, no link, regs @ 0xfe200000
> PCIe1: Bus 00 - 00
> PCIe2: disabled
> PCIe3: Root Complex, no link, regs @ 0xfe202000
> PCIe3: Bus 01 - 01
> PCIe4: disabled
> In:    serial
> Out:   serial
> Err:   serial
> Net:   Initializing Fman
> Fman1: Uploading microcode version 106.1.7
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out
> FM1 at DTSEC1, FM1 at DTSEC2, FM1 at DTSEC3, FM1 at DTSEC4, FM1 at DTSEC5, FM1 at TGEC1
> Hit any key to stop autoboot:  0
> =>
>
> Cheers,
> Ben.
>
>
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