[PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and secondary CPUs

[Benjamin Herrenschmidt]

On Mon, 2013-03-04 at 20:46 +1100, Michael Neuling wrote:
> Currently we only set the FSCR when HV=1 but this feature is available when
> HV=0 also.  This patch sets FSCR when HV=0.
> 
> Also, we currently only set the FSCR on the master CPU.  This patch also sets
> the FSCR on secondary CPUs.

Please add a quick blurb/reminder of what FSCR is (at least expand the
accronym).

Cheers,
Ben.

> Signed-off-by: Michael Neuling <mikey at neuling.org>
> cc: Ian Munsie <imunsie at au1.ibm.com>
> ---
>  arch/powerpc/kernel/cpu_setup_power.S |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
> index d29facb..bb2d203 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.S
> +++ b/arch/powerpc/kernel/cpu_setup_power.S
> @@ -48,6 +48,7 @@ _GLOBAL(__restore_cpu_power7)
>  
>  _GLOBAL(__setup_cpu_power8)
>  	mflr	r11
> +	bl	__init_FSCR
>  	bl	__init_hvmode_206
>  	mtlr	r11
>  	beqlr
> @@ -56,13 +57,13 @@ _GLOBAL(__setup_cpu_power8)
>  	mfspr	r3,SPRN_LPCR
>  	oris	r3, r3, LPCR_AIL_3 at h
>  	bl	__init_LPCR
> -	bl	__init_FSCR
>  	bl	__init_TLB
>  	mtlr	r11
>  	blr
>  
>  _GLOBAL(__restore_cpu_power8)
>  	mflr	r11
> +	bl	__init_FSCR
>  	mfmsr	r3
>  	rldicl.	r0,r3,4,63
>  	beqlr