Detecting LD/ST instruction

[Michael Neuling]

Sukadev Bhattiprolu <sukadev at linux.vnet.ibm.com> wrote:

> Michael Neuling [mikey at neuling.org] wrote:
> | > I am working on implementing the 'perf mem' command for Power
> | > systems. This would for instance, let us know where in the memory
> | > hierarchy (L1, L2, Local RAM etc) the data for a load/store
> | > instruction was found (hit).
> | > 
> | > On Power7, if the mcmcra[DCACHE_MISS] is clear _and_ the
> | > instruction is a load/store, then it implies a L1-hit.
> | > 
> | > Unlike on Power8, the Power7 event vector has no indication
> | > if the instruction was load/store.
> | > 
> | > In the context of a PMU interrupt, is there any way to determine
> | > if an instruction is a load/store ?
> | 
> | You could read the instruction from memory and work it out.  
> | 
> | We do something similar to this in power_pmu_bhrb_to() where we read the
> | instruction and work out where the branch is going to.
> | 
> | If you do this, please use and/or extend the functions in
> | arch/powerpc/lib/code-patching.c
> 
> Here is a draft of what I could come up with.  With this patch, 
> the number of L1 hits on Power7 matches that on Power8 for one
> application.

Nice, the approach is along the lines of what I was thinking.

> But, wondering if there is a more efficient way to do this - there
> are over 50 flavors of load and store!

I dunno, there might be.  If you look at all the opcodes in binary,
there's often a nice little pattern you can use. 

Did you catch all the VSX and VMX loads/stores?

<snip>
> +	if (op == 31) {
> +		n = sizeof(x_form_load_store) / sizeof(int);
> +
> +		for (i = 0; i < n; i++) {

Yeah, this might be a bit slow... Are there any instructions with op ==
31 that aren't a load/store?

> 
> +			if (x_form_load_store[i] == load_store_xval(*instr))
> +				return 1;
> +		}
> +	}
> +
> +	return 0;
> +}