[PATCH] powerpc: add the missing required isync for the coherent icache flush

[Kevin Hao]

On Wed, Aug 21, 2013 at 07:28:54AM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2013-08-20 at 20:16 +0800, Kevin Hao wrote:
> 
> > Dummy question: What does the ifetch buffers mean? The instruction fetch
> > pipeline or instruction dispatch pipeline? Shouldn't all the prefetched
> > instructions in these buffers be discarded by isync?
> 
> Architecturally isync doesn't have to toss prefetch completely. It only
> needs to make sense that context changes performed by previous
> instructions (and interrupts/traps) happen at the point of the isync,
> for example, it will ensure that a trap conditional is fully evaluated
> before subsequent instruction execution, etc....
> 
> So in this case, it makes sure the icbi has been executed and it's the
> icbi that invalidates the prefetched instructions.
> 
> > 
> > >, sync orders the icbi and isync ensures its execution has been
> > > synchronized. At least I *think* that's the required sequence, I have to
> > > dbl check the arch, maybe tomorrow. I wouldn't be surprise if we also
> > > need a sync before the icbi to order the actual stores to memory that
> > > might have modified instructions with the icbi.
> > 
> > Doesn't the coherence between icache and dcache be maintained by the snooping?
> 
> The icache yes, but not the ifetch buffers (basically think of them as
> buffering stages between icache and dispatch). At least that's my
> understanding of the implementation. 

OK. Thanks for the explanation. I will update the patch according to your
suggestions.

Thanks,
Kevin
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