[PATCH] powerpc: add the missing required isync for the coherent icache flush

[Wang Dongsheng-B40534]

> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+b40534=freescale.com at lists.ozlabs.org] On Behalf Of Kevin Hao
> Sent: Thursday, August 15, 2013 7:56 PM
> To: Benjamin Herrenschmidt
> Cc: linuxppc
> Subject: [PATCH] powerpc: add the missing required isync for the coherent
> icache flush
> 
> Even we don't need to flush the dcache and invalidate the icache
> on the CPU which has coherent icache. But we do need an isync to
> discard the prefetched instructions in this case.
> 
> Signed-off-by: Kevin Hao <haokexin at gmail.com>
> ---
>  arch/powerpc/kernel/misc_32.S | 2 ++
>  arch/powerpc/kernel/misc_64.S | 1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/arch/powerpc/kernel/misc_32.S
> b/arch/powerpc/kernel/misc_32.S
> index 777d999..0b84c8d 100644
> --- a/arch/powerpc/kernel/misc_32.S
> +++ b/arch/powerpc/kernel/misc_32.S
> @@ -433,6 +433,7 @@ _GLOBAL(invalidate_dcache_range)
>   */
>  _GLOBAL(__flush_dcache_icache)
>  BEGIN_FTR_SECTION
> +	isync
There is not touch the icache, why need we to do this?

>  	blr
>  END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
>  	rlwinm	r3,r3,0,0,31-PAGE_SHIFT		/* Get page base address
> */
> @@ -474,6 +475,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
>   */
>  _GLOBAL(__flush_dcache_icache_phys)
>  BEGIN_FTR_SECTION
> +	isync
>  	blr					/* for 601, do nothing */
>  END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
>  	mfmsr	r10
> diff --git a/arch/powerpc/kernel/misc_64.S
> b/arch/powerpc/kernel/misc_64.S
> index 992a78e..d74fefb 100644
> --- a/arch/powerpc/kernel/misc_64.S
> +++ b/arch/powerpc/kernel/misc_64.S
> @@ -69,6 +69,7 @@ PPC64_CACHES:
> 
>  _KPROBE(flush_icache_range)
>  BEGIN_FTR_SECTION
> +	isync
>  	blr
>  END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
>  /*
> --
> 1.8.3.1
> 
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