[3/3,v2] powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3

[Scott Wood]

On Fri, Jun 21, 2013 at 06:59:14PM +0800, Minghuan Lian wrote:
> The original MPIC MSI bank contains 8 registers, MPIC v4.3 MSI bank
> contains 16 registers, and this patch adds NR_MSI_REG_MAX and
> NR_MSI_IRQS_MAX to describe the maximum capability of MSI bank.
> MPIC v4.3 provides MSIIR1 to index these 16 MSI registers. MSIIR1
> uses different bits definition than MSIIR. This patch adds
> ibs_shift and srs_shift to indicate the bits definition of the
> MSIIR and MSIIR1, so the same code can handle the MSIIR and MSIIR1
> simultaneously.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com>
> 
> ---
> v2 log:
> 1. remove 'msiregs' support.
> 
>  arch/powerpc/sysdev/fsl_msi.c | 132 ++++++++++++++++++++++++++++++------------
>  arch/powerpc/sysdev/fsl_msi.h |  10 +++-
>  2 files changed, 101 insertions(+), 41 deletions(-)

Applied with the following changes:

diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index fd6458b..77efbae 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -481,8 +481,8 @@ static int fsl_of_msi_probe(struct platform_device *dev)
 				goto error_out;
 		}
 	} else {
-		const u32 all_avail[] = { 0,
-					  NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG};
+		static const u32 all_avail[] =
+			{ 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
 
 		msi->srs_shift = MSIIR_SRS_SHIFT;
 		msi->ibs_shift = MSIIR_IBS_SHIFT;


-Scott