[1/3,v2] powerpc/dts: update MSI bindings doc for MPIC v4.3
scottwood at freescale.com
Thu Aug 8 10:30:21 EST 2013
On Fri, Jun 21, 2013 at 06:59:12PM +0800, Minghuan Lian wrote:
> Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
> MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
> 16 MSI registers, but uses different IBS and SRS shift. When using
> MSIR1, the interrupt number is not consecutive. It is hard to use
> 'msi-available-ranges' to describe the ranges of the available
> interrupt, so MPIC v4.3 does not support this property.
> Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com>
> v2 log:
> 1. move msi-available-ranges to optional properties.
> .../devicetree/bindings/powerpc/fsl/msi-pic.txt | 51 +++++++++++++++++-----
> 1 file changed, 40 insertions(+), 11 deletions(-)
Applied with these changes:
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index d82b080..82dd5b6 100644
@@ -1,13 +1,13 @@
* Freescale MSI interrupt controller
-- compatible : compatible list, may contains one or two entries,
- first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
+- compatible : compatible list, may contain one or two entries
+ The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
"fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
- provided to access these 16 registers, compatible "fsl,mpic-msi-v4.3"
- should be used. The first entry is optional, the second entry must be
+ provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
+ should be used. The first entry is optional; the second entry is
- reg : It may contain one or two regions. The first region should contain
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