flush_icache_range on AMCC 44x targets

[Mike]

Hi,

i was reading trough arch/powerpc/kernel/misc32.S looking at the icbi and
iccci instructions, from whats on print in
http://s.eeweb.com/members/kvks_kumar/answers/1356585717-PPC440_UM2013.pdf(page
272) iccci should be used once in the power-on / reset routine, and
as far as flush_icache_range goes presumably before icbi is called?

So should not flush_icache_range go
#ifdef CONFIG_44x
iccci    0, r0
#endif
icbi    0,r6

arch/powerpc/kernel/misc32.S:
/*
 * Write any modified data cache blocks out to memory
 * and invalidate the corresponding instruction cache blocks.
 * This is a no-op on the 601.
 *
 * flush_icache_range(unsigned long start, unsigned long stop)
 */
_KPROBE(__flush_icache_range)
BEGIN_FTR_SECTION
    blr                /* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
    li    r5,L1_CACHE_BYTES-1
    andc    r3,r3,r5
    subf    r4,r3,r4
    add    r4,r4,r5
    srwi.    r4,r4,L1_CACHE_SHIFT
    beqlr
    mtctr    r4
    mr    r6,r3
1:    dcbst    0,r3
    addi    r3,r3,L1_CACHE_BYTES
    bdnz    1b
    sync                /* wait for dcbst's to get to ram */
#ifndef CONFIG_44x
    mtctr    r4
2:    icbi    0,r6
    addi    r6,r6,L1_CACHE_BYTES
    bdnz    2b
#else
    /* Flash invalidate on 44x because we are passed kmapped addresses and
       this doesn't work for userspace pages due to the virtually tagged
       icache.  Sigh. */
    iccci    0, r0
#endif
    sync                /* additional sync needed on g4 */
    isync
    blr


Best regards
-Mike
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