[PATCH 4/5] powerpc/powernv: Patch MSI EOI handler on P8

[Gavin Shan]

On Wed, Apr 24, 2013 at 01:21:53AM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-04-23 at 19:03 +0800, Gavin Shan wrote:
>> 
>> +static int pnv_pci_ioda_msi_eoi(struct pnv_phb *phb, unsigned int hw_irq)
>> +{
>> +       u8 p_bit = 1, q_bit = 1;
>> +       long rc;
>> +
>> +       while (p_bit || q_bit) {
>> +               rc = opal_pci_get_xive_reissue(phb->opal_id,
>> +                               hw_irq - phb->msi_base, &p_bit, &q_bit);
>> +               if (rc) {
>> +                       pr_warning("%s: Failed to get P/Q bits of IRQ#%d "
>> +                                  "on PHB#%d, rc=%ld\n", __func__, hw_irq,
>> +                                  phb->hose->global_number, rc);
>> +                       return -EIO;
>> +               }
>> +               if (!p_bit && !q_bit)
>> +                       break;
>> +
>> +               rc = opal_pci_set_xive_reissue(phb->opal_id,
>> +                               hw_irq - phb->msi_base, p_bit, q_bit);
>> +               if (rc) {
>> +                       pr_warning("%s: Failed to clear P/Q (%01d/%01d) of "
>> +                                  "IRQ#%d on PHB#%d, rc=%ld\n", __func__,
>> +                                  p_bit, q_bit, hw_irq,
>> +                                  phb->hose->global_number, rc);
>> +                       return -EIO;
>> +               }
>> +       }
>> +
>> +       return 0;
>> +}
>
>Can you turn that into a single opal_pci_msi_eoi() ? This means that a
>single MSI will trigger only one OPAL call rather than two which is
>better for performances.
>

Ok. I will add new OPAL API opal_pci_msi_eoi() and use that in next version.

>We will later implement an "optimized" variant using direct MMIO based
>on knowing specifically the HW type but not now.
>

Ok :-)

Thanks,
Gavin