[PATCH] powerpc/perf: Add missing L2 constraint handling in Power7 PMU

Paul Mackerras paulus at samba.org
Wed Oct 31 15:18:34 EST 2012

On Wed, Oct 31, 2012 at 01:09:56PM +1100, Michael Ellerman wrote:
> If we have two cache events that require different settings of the L2SEL
> bits in MMCR1 then we can not schedule those events simultaneously. Add
> logic to the constraint handling to express that.
> Signed-off-by: Michael Ellerman <michael at ellerman.id.au>

Acked-by: Paul Mackerras <paulus at samba.org>

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