fsl spi questions & patch

[Frans Meulenbroeks]

Hi,

I've been playing with spi on mpc8313e and have some things on
spi-fsl-spi.c:

Is QE useful on 8313?
I've tried it (using cpu-qe in my dts file) and see in the boot log that it
is used, but I do not really see any effect when it comes to performance or
cpu usage.

Furthermore:
In the fsl_spi_cpu_irq there is a line:
        /* Clear the events */
        mpc8xxx_spi_write_reg(&reg_base->event, events);

Is this really useful? The 8313 book says NE is cleared upon reading and NF
is cleared upon writing.
(this might apply to fsl_spi_cpm_irq too, I do not have info on cpm.

Next, I noticed some spacing between two spi words being sent. It seems the
transmit buffer is not filled when possible, but only when a word is
received (and the previous word is transmitted). By modifying the code
somewhat I was able to roughly double the effective transfer rate in my
test setup (8 Mhz spi clock, 32 bit transfers). Attached is my changed
code. Feedback on it is appreciated.

This patch also eliminated the spinning until TX is done. (actually I am
not sure if this will happen, I would expect NE and NF to be raised roughly
at the same time.

Thanks for any feedback!

Frans Meulenbroeks

PS:it would probably be nice if in board setup one could also set the
(default) value of bits-per-word.
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