[PATCH 4/4] powerpc/mpic: FSL MPIC error interrupt support.
B16395 at freescale.com
Tue Jun 19 05:12:30 EST 2012
> >>> + * Error interrupt registers
> >>> + */
> >>> +
> >>> +#define MPIC_ERR_INT_BASE 0x3900
> >>> +#define MPIC_ERR_INT_EISR 0x0000
> >>> +#define MPIC_ERR_INT_EIMR 0x0010
> >>> +
> >>> #define MPIC_MAX_IRQ_SOURCES 2048
> >>> #define MPIC_MAX_CPUS 32
> >>> #define MPIC_MAX_ISU 32
> >>> #define MPIC_MAX_TIMER 8
> >>> #define MPIC_MAX_IPI 4
> >>> +#define MPIC_MAX_ERR 32
> >> Should probably be 64
> > This patch supports MPIC 4.1 and EISR0. When support is added for
> > EISR1 (didn't realize this was coming until your comment prompted me
> > to check...), this should be updated, but this change alone would not
> > make it work.
> Would prefer we handle this now rather than later (T4240 is going to need
> EISR1 support).
As of now I don't have a proper mechanism to test this functionality. I will
submit a follow up patch for EISR1/EIMR1 support once I have a mechanism to
test this functionality.
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