[PATCH 2/2] powerpc/e6500: TLB miss handler with hardware tablewalk support

[Scott Wood]

On 06/14/2012 08:05 PM, Benjamin Herrenschmidt wrote:
>>  - It has threads, but no "tlbsrx." -- so we need a spinlock and
>>    a normal "tlbsx".  Because we need this lock, hardware tablewalk
>>    is mandatory on e6500 unless we want to add spinlock+tlbsx to
>>    the normal bolted TLB miss handler.
> 
> Isn't this a violation of the architecture ? (Isn't tlbsrx. mandatory ?
> in 2.06 MAV2 ?).

I don't think so -- not only does it have a category name, there's a
MAV2-specific bit in MMUCSR indicating whether the category is present.

I still don't understand why Freescale omitted it from a chip that has
threads, though.

-Scott