Question about MPIC_SINGLE_DEST_CPU on P1020 (e500 core) SMP
r58472 at freescale.com
Mon Jun 11 19:36:53 EST 2012
> Subject: Question about MPIC_SINGLE_DEST_CPU on P1020 (e500 core) SMP
> The P1020 manual states (in the PIC chapter) that in the "Internal
> Interrupt Destination" register, only 1 CPU (and not both) can be
> selected as the IRQ destination. How then can we achieve "interrupt
> spraying" for the PCI interrupt (we want interrupts to be sent
> alternately to CPU0 and CPU1). Also, we changed the code to ignore the
> MPIC_SINGLE_DEST_CPU flag and set both CPUs in the destination of the
> PIC_IIDRn register. This does seem to work. But we're not sure if we can
> rely on this behavior and whether it will cause other problems.
I suggest you to follow the UM. The note should be there for a reason although personally I don't know what the specific problem will be.
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