[PATCH] powerpc/fsl: mpic timer driver

[Wang Dongsheng-B40534]

> -----Original Message-----
> From: Kumar Gala [mailto:galak at kernel.crashing.org]
> Sent: Friday, July 27, 2012 9:14 PM
> To: Wang Dongsheng-B40534
> Cc: benh at kernel.crashing.org; paulus at samba.org; Wood Scott-B07421;
> linuxppc-dev at lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/fsl: mpic timer driver
> 
> 
> On Jul 27, 2012, at 1:20 AM, <Dongsheng.wang at freescale.com>
> <Dongsheng.wang at freescale.com> wrote:
> 
> > From: Wang Dongsheng <Dongsheng.Wang at freescale.com>
> >
> > Global timers A and B internal to the PIC. The two independent groups
> > of global timer, group A and group B, are identical in their
> functionality.
> > The hardware timer generates an interrupt on every timer cycle.
> > e.g
> > Power management can use the hardware timer to wake up the machine.
> >
> > Signed-off-by: Wang Dongsheng <Dongsheng.Wang at freescale.com>
> > Signed-off-by: Li Yang <leoli at freescale.com>
> 
> How much of this is FSL specific vs openpic?  OpenPIC spec's timer
> support (only a single group).
> 
[Wang Dongsheng] Yes, OpenPIC only a single group timer.
FSL: add more register, features and group.
This patch only to support FSL chip.
"mpic_timer.c" -> "fsl_mpic_timer.c"
I will modify the description of the patch. how about?

 > > +static int set_cascade_timer(struct group_priv *priv, u64 ticks,
> > +		unsigned int num)
> > +{
> > +	struct cascade_priv *casc_priv;
> > +	u32 tmp;
> > +	u32 tmp_ticks;
> > +	u32 rem_ticks;
> > +
> > +	/* set group tcr reg for cascade */
> > +	casc_priv = priv->timer[num].cascade_handle;
> > +	if (!casc_priv)
> > +		return -EINVAL;
> > +
> > +	tmp = casc_priv->tcr_value |
> > +		(casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
> > +	setbits32(priv->group_tcr, tmp);
> > +
> > +	tmp_ticks = div_u64_rem(ticks, MAX_TIME_CASCADE, &rem_ticks);
> > +
> > +	out_be32(&priv->regs[num].gtccr, 0);
> > +	out_be32(&priv->regs[num].gtbcr, tmp_ticks | MPIC_TIMER_STOP);
> > +
> > +	out_be32(&priv->regs[num - 1].gtccr, 0);
> > +	out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);
> > +
> > +	return 0;
> > +}
> > +
> > +struct mpic_timer *get_cascade_timer(u64 ticks) {
> 
> should this be static?
> 
[Wang Dongsheng] ok.

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