[PATCH] eSDHC: Access Freescale eSDHC registers by 32-bit

Anton Vorontsov cbouatmailru at gmail.com
Sat Sep 10 00:07:01 EST 2011

On Fri, Sep 09, 2011 at 08:05:46PM +0800, Roy Zang wrote:
> From: Xu lei <B33228 at freescale.com>
> Freescale eSDHC registers only support 32-bit accesses,
> this patch ensures that all Freescale eSDHC register accesses
> are 32-bit.
> Signed-off-by: Xu lei <B33228 at freescale.com>
> Signed-off-by: Roy Zang <tie-fei.zang at freescale.com>
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
> ---

The patch looks OK.

Acked-by: Anton Vorontsov <cbouatmailru at gmail.com>

> +static u8 esdhc_readb(struct sdhci_host *host, int reg)
> +{
> +	int base = reg & ~0x3;
> +	int shift = (reg & 0x3) * 8;
> +	u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
>  	return ret;
>  }

Though, I wonder if we could change sdhci_be32bs_read{b,w}, instead
of making this local to eSDHC.

The thing is: sdhci_be32bs_writeb() is using clrsetbits_be32,
so the write variant already uses 32-bit accessors, so nothing should
break if we switch sdhci_be32bs_readb() to in_be32().

But maybe it's safer if we do this in a separate patch, so that it
could be easily reverted without impacting eSDHC if something actually

You decide. :-)


Anton Vorontsov
Email: cbouatmailru at gmail.com

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