[PATCH] perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events

[Michael Neuling]

> perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events
> 
> 	Extent the POWER7 PMU driver with definitions
> 	for generic front-end and back-end stall events.

Anshuman,

Can you explain what these P7 events actually are and how they relate to
Ingo's original comment on this in
8f62242246351b5a4bc0c1f00c0c7003edea128a

    Both events limit performance: most front end stalls tend to be
    caused by branch misprediction or instruction fetch cachemisses,
    backend stalls can be caused by various resource shortages or
    inefficient instruction scheduling.

> 
> Signed-off-by: Anshuman Khandual <khandual at linux.vnet.ibm.com>
> 
> diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c
> index 593740f..e5d2844 100644
> --- a/arch/powerpc/kernel/power7-pmu.c
> +++ b/arch/powerpc/kernel/power7-pmu.c
> @@ -297,6 +297,8 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
>  
>  static int power7_generic_events[] = {
>  	[PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
> +	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */

eg. Is this Global Completion Table (GCT) empty?

> +	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a,  /* CMPLU_STALL */

eg. Is this instruction completion stall?

Mikey

>  	[PERF_COUNT_HW_INSTRUCTIONS] = 2,
>  	[PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880,	/* LD_REF_L1_LSU*/
>  	[PERF_COUNT_HW_CACHE_MISSES] = 0x400f0,		/* LD_MISS_L1	*/
> 
> -- 
> Anshuman Khandual 
> 
> 
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