[PATCH 1/7] powerpc/85xx: re-enable timebase sync disabled by KEXEC patch

[Li Yang-R58472]

>-----Original Message-----
>From: linuxppc-dev-bounces+leoli=freescale.com at lists.ozlabs.org
>[mailto:linuxppc-dev-bounces+leoli=freescale.com at lists.ozlabs.org] On
>Behalf Of Scott Wood
>Sent: Saturday, November 05, 2011 1:34 AM
>To: Zhao Chenhui-B35336
>Cc: linuxppc-dev at lists.ozlabs.org
>Subject: Re: [PATCH 1/7] powerpc/85xx: re-enable timebase sync disabled by
>KEXEC patch
>
>On 11/04/2011 07:29 AM, Zhao Chenhui wrote:
>> From: Li Yang <leoli at freescale.com>
>>
>> The timebase sync is not only necessary when using KEXEC. It should also
>> be used by normal boot up and cpu hotplug. Remove the ifdef added by
>> the KEXEC patch.
>
>The KEXEC patch didn't just add the ifdef, it also added the initializers:

Yes.  But the code suggests that the timebase synchronization is only necessary for KEXEC, but it turns out that sleep/wakeup also need it.  Maybe the description of the patch need to be changed as KEXEC is not to be blamed.

>
>> @@ -105,8 +107,64 @@ smp_85xx_setup_cpu(int cpu_nr)
>>
>>  struct smp_ops_t smp_85xx_ops = {
>>         .kick_cpu = smp_85xx_kick_cpu,
>> +#ifdef CONFIG_KEXEC
>> +       .give_timebase  = smp_generic_give_timebase,
>> +       .take_timebase  = smp_generic_take_timebase,
>> +#endif
>>  };
>
>U-Boot synchronizes the timebase on 85xx.  With what chip and U-Boot
>version are you seeing this not happen?

I'm curious why don't we make it happen in kernel as we are against adding dependency to the bootloader?  Other architectures don't have this dependency, it will be better if we don't add this dependency either IMO.


>
>If you are seeing only a small (around one tick) difference, make sure
>you're running a U-Boot that has this commit:
>
>> commit 7afc45ad7d9493208d89072cbb78a5bfc8034b59
>> Author: Kumar Gala <galak at kernel.crashing.org>
>> Date:   Sun Mar 13 10:55:53 2011 -0500
>>
>>     powerpc/85xx: Fix synchronization of timebase on MP boot
>>
>>     There is a small ordering issue in the master core in that we need
>to
>>     make sure the disabling of the timebase in the SoC is visible before
>we
>>     set the value to 0.  We can simply just read back the value to
>>     synchronizatize the write, before we set TB to 0.
>>
>>     Reported-by: Dan Hettena
>>     Tested-by: Dan Hettena
>>     Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
>
>
>-Scott
>
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