[PATCH 2/7] powerpc/mm: 64-bit 4k: use a PMD-based virtual page table

[Scott Wood]

On Tue, 24 May 2011 06:51:01 +1000
Benjamin Herrenschmidt <benh at kernel.crashing.org> wrote:

> Is your linear mapping bolted ? If it is you may be able to cut out most
> of the save/restore stuff (SRR0,1, ...) since with a normal walk you
> won't take nested misses.

It is bolted -- we ignore anything we can't map with 16 entries.  The only
semi-realistic case I can think of where we might bump into that (and thus
want non-bolted memory), especially with more than negligible loss compared
to the size of memory, is AMP with a non-zero start address where we have
to stick with smaller pages due to alignment. Even so, 16 times the
alignment of the start of RAM doesn't seem that unreasonable a limit.  The
32-bit limit of 3 entries for lowmem is a bit more troublesome there.

-Scott