[PATCH 0/1] ppc4xx: Fix PCIe scanning for the 460SX

[Ayman El-Khashab]

On Tue, May 31, 2011 at 02:27:19PM -0700, Tirumala Marri wrote:
> Not sure how I would know --  But with my eiger kit, I got a
> cd from amcc that had a patched 2.6.30 or something kernel
> in it to support the 460SX.  The pci code was basically
> subverted by adding a "port->link=1" at the very end of the
> link check to always force it to succeed.  However this code
> never appeared in the public git repositories, so I am not
> sure how the 460SX functioned (if it ever did) since the
> link check that is in there now can't work on that SOC.
> 
> 
> [marri]I don't know what PCI-E devices you use. We use E1000
> As a device for testing. Link-up was working before the submission.
> There were some changes happened afterwards to the common code
> Which seems to affected all 4xx devices. I will try latest code
> On our other SoCs.

Well, briefly we build a custom processor board that has
a couple powerpcs on it and some pcie switches.  We end up
plugging our devices into the switches which is unlike what
most people try.  In any case, we use several different
drive controllers for SAS, SCSI, and SSDs.  For testing
purposes (i.e. when things don't go the way they should) we
have an adapter to make "regular" pcie slots that we plug in
whatever.  But our switches are on the board with the CPUs
so as far as the CPU goes, it will always see a gen-2 link
8 lane link, irrespective of what the endpoint actually is.
We let the switches handle the speed changes and the port
bifurcation.  

> I took care of that in my patch.  Basically it let the
> system go to gen-2 speeds and negotiate down.
> [marri] Great thx.

Ok, so I am back from doing whatever it is that I do.  Shall
I go ahead and take a stab at making a new functor to handle
the "link check"? -- which IIRC was the thought from last
month about how best to handle the 460SX and whatever some
people were using internally.

Ayman