[PATCH 06/15] 8xx: Always pin kernel instruction TLB

Dan Malek ppc6dev at digitaldans.com
Wed Jun 15 02:06:45 EST 2011

Hi Joakim.

On Jun 14, 2011, at 6:54 AM, Joakim Tjernlund wrote:

> Various kernel asm modifies SRR0/SRR1 just before executing
> a rfi. .....

I'm going to argue we can easily visually inspect for this
since the code is static with just a couple of RFIs in these
exception handlers.

Some 8xx processors have few TLB entries, and always taking
one for the kernel, especially if it isn't needed, could have a
detrimental effect on the application performance.  Even the
"big" 8xx processors don't have that many entries.  Some
benchmarks run on an MPC850 would likely show this.

Anyone making modifications to this level of software should
know of this problem, or make it known in a comment.  If you
are making changes, just compile the code and manually
check it with the couple of configuration options that affect
the placement of the instructions.

The better solution would be supporting large page sizes,
at least for the kernel.


	-- Dan

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