Problem with eLBC?

[Joakim Tjernlund]

>
> On 12/05/2011 08:02 AM, Alexander Lyasin wrote:
> > In reply to your Service Request SR 1-807899446:
> >
> > Yes, due to several design peculiarities in local bus nand controller,
> > simultaneous accesses to nand flash and to other local bus memory
> > controller may cause nand flash controller access failure. Our linux
> > team suggested to use "software lock" method to avoid this problem -
> > please do not use other local bus controllers, when nand flash is accessed.
>
> What kernel version are you using?  The latest mainline kernel should
> not have this issue.
>
> Make sure you have these patches:
>
> commit d08e44570ed611c527a1062eb4f8c6ac61832e6e
> Author: Shengzhou Liu <Shengzhou.Liu at freescale.com>
> Date:   Thu May 19 18:48:01 2011 +0800
>
>     powerpc/fsl_lbc: Add workaround for ELBC-A001 erratum
>
>     Simultaneous FCM and GPCM or UPM operation may erroneously trigger
>     bus monitor timeout.
>
>     Set the local bus monitor timeout value to the maximum by setting
>     LBCR[BMT] = 0 and LBCR[BMTPS] = 0xF.
>
>     Signed-off-by: Shengzhou Liu <Shengzhou.Liu at freescale.com>
>     Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
>
> and
>
> commit 476459a6cf46d20ec73d9b211f3894ced5f9871e
> Author: Scott Wood <scottwood at freescale.com>
> Date:   Fri Nov 13 14:13:01 2009 -0600
>
>     mtd: eLBC NAND: use recommended command sequences
>
>     Currently, the program and erase sequences do not wait for completion,
>     instead relying on a subsequent waitfunc() callback.  However, this
> causes
>     the chipselect to be deasserted while the NAND chip is still
> asserting the
>     busy pin, which can corrupt activity on other chipselects.
>
>     This patch switches to using the sequences recommended by the manual,
>     in which a wait is performed within the initial command sequence.
> We can
>     now re-use the status byte from the initial command sequence, rather
> than
>     having to do another status read in the waitfunc.
>
>     Since we're already touching the command sequences, it also cleans
> up some
>     cruft in SEQIN that isn't needed since we cannot program partial pages
>     outside of OOB.
>
>     Signed-off-by: Scott Wood <scottwood at freescale.com>
>     Reported-by: Suchit Lepcha <suchit.lepcha at freescale.com>
>     Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy at nokia.com>
>     Signed-off-by: David Woodhouse <David.Woodhouse at intel.com>
>
> -Scott

Scott, you seem know something about eLBC and NAND. I have been told
that using NAND and other memory mapped devices on the same LB may
stall accesses to the other devices as the FCM may hold the bus for
long periods(a whole write or erase op.), is this so?

If still true, I guess the whole CPU "freezes" until the NAND op.
is complete?

 Jocke