[PATCH 2/2] powerpc/85xx: add a 32-bit P1022DS device tree
Scott Wood
scottwood at freescale.com
Sat Dec 3 09:19:33 EST 2011
On 12/02/2011 04:08 PM, Timur Tabi wrote:
> + lbc: localbus at ffe05000 {
> + reg = <0x0 0xffe05000 0 0x1000>;
> + ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
> + 0x1 0x0 0x0 0xe0000000 0x08000000
> + 0x2 0x0 0x0 0xff800000 0x00040000
> + 0x3 0x0 0x0 0xffdf0000 0x00008000>;
> +
> + /*
> + * This node is used to access the pixis via "indirect" mode,
> + * which is done by writing the pixis register index to chip
> + * select 0 and the value to/from chip select 1. Indirect
> + * mode is the only way to access the pixis when DIU video
> + * is enabled. Note that this assumes that the first column
> + * of the 'ranges' property above is the chip select number.
> + */
> + board-control at 0,0 {
> + compatible = "fsl,p1022ds-indirect-pixis";
> + reg = <0x0 0x0 1 /* CS0 */
> + 0x1 0x0 1>; /* CS1 */
> + };
> +
> + nor at 0,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "cfi-flash";
> + reg = <0x0 0x0 0x8000000>;
> + bank-width = <2>;
> + device-width = <1>;
[snip]
> + };
> +
> + nand at 2,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,elbc-fcm-nand";
> + reg = <0x2 0x0 0x40000>;
[snip]
> + };
> + };
> +
> + board-control at 3,0 {
> + compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
> + reg = <3 0 0x30>;
> + interrupt-parent = <&mpic>;
> + /*
> + * IRQ8 is generated if the "EVENT" switch is pressed
> + * and PX_CTL[EVESEL] is set to 00.
> + */
> + interrupts = <8 8 0 0>;
> + };
> + };
[snip]
> +/include/ "fsl/p1022si-post.dtsi"
Please add something after post to strip simple-bus off of the localbus
node's compatible. Either you have board-control at 0,0, or you have the
other stuff (did you ever find out what the situation with NAND is?) --
not both at the same time. Or do you have U-Boot patching in status
updates now?
I realize this isn't a 32-bit versus 36-bit issue, but this seemed as
good a time as any to repeat this complaint. :-)
-Scott
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