P1021MDS QE Ethernet Ports
johnkokko at hotmail.com
Fri Sep 3 17:05:17 EST 2010
> Subject: RE: P1021MDS QE Ethernet Ports
> From: Haiying.Wang at freescale.com
> To: johnkokko at hotmail.com
> CC: linuxppc-dev at lists.ozlabs.org
> Date: Thu, 2 Sep 2010 09:32:48 -0400
> On Thu, 2010-02-09 at 11:26 +0300, Ioannis Kokkoris wrote:
>>> From: johnkokko at hotmail.com
>>> To: linuxppc-dev at lists.ozlabs.org
>>> Subject: P1021MDS QE Ethernet Ports
>>> Date: Wed, 1 Sep 2010 15:11:56 +0300
>>> we are seeing a strange behavior when trying to use the QE Ethernet interfaces.
>>> ENET5 (UCC5 - RMII) interface on P1021MDS boards does not come up if there is no physical link on the ENET1 (UCC1 - MII) Port.
>>> It seems that interrupts from ENET5 are normally received but the link comes up and works properly only if we have physical connection on ENET1.
>> So far I found the following:
>> After adding traces, it seems that genphy_update_link() polls the correct device, with the correct address (0x03), but although a physical link is present in ENET5, the polling is not successful until there is a link in ENET1 (address 0x02)!
>> genphy_update_link: Dev: Micrel KS8041 ADD: 3 Status read 0x7849 (without ENET1 Link)
>> genphy_update_link: Dev: Micrel KS8041 ADD: 3 Status read 0x786D (with ENET1 Link)
>> How does the MDIO of ENET1 affect the management of the physical interface in a different HW address?
> Which board version are you using? this problem is now fixed in the new board version but not available right now.
We are using a board revision 2 (pilot version). Our main concern is whether this issue affects the working UCC1 eth interface performance.
Do you think that removing or pulling-down R79 (pin 21 at U11) will fix the problem with ENET1?
> You can connect two UECs for your current development.
Do you mean that changing the ENET1 interface from UCC1 to UCC3 in dts may solve the problem?
thank you for your reply,
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