Support for multiple port's

[Thomas Taranowski]

Going through the code, it looks like the rapidio driver assumes
there's only going to be a single Port implemented.

Snapshot of code assumes a single port atmu configuration block, which
is wrong for the p2020, and probably other QorIQ processors.

<snip>
priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
					+ RIO_ATMU_REGS_OFFSET);
priv->maint_atmu_regs = priv->atmu_regs + 1;
priv->dbell_atmu_regs = priv->atmu_regs + 2;
priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
			((port->phy_type == RIO_PHY_SERIAL) ?
			RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
<snip>

On the newer QorIQ P2020 processors there are 2 sets of port
registers, so the current code lays the dbell_atmu_regs structure on
top of the second set of atmu_regs.  There are probably other issues
as well.

Are there any patch sets available that support the newer processors,
and multi-port ( multi-homed? ) RapidIO configurations?

Thanks!