Freescale P2020 / 85xx PCIe and Advance Error Reporting (AER) service problem

[Kumar Gala]

On Oct 7, 2010, at 7:30 AM, Eran Liberty wrote:

> Dear Penguins,
> 
> SHORT:
> There is a BUG in the current code design / Freescale P2020/85xx PCIe design that prevent it from registering to the PCIe AER... or that I have missed something :) ..
> 
> LESS SHORT:
> I am in the process of a Freescale P2020 based board bring up. P2020 is basically two 85xx processors and their peripherals share most features.
> 
> PCIe has a very extensive error reporting section and the Kernel already has a very nice looking Advanced Error Reporting driver.
> 
> I encounter difficulties trying to connect the P2020/85xx PCIe device to this AER service driver.
> 
> My technical findings follows:
> 
> - pcie_portdrv_probe() will be called for every BRIDGE class PCI device. P2020 PCIe is a PCI-PCI BRIDGE class so no problem here. - The code will continue to check that we have PCI_CAP_ID_EXP capability, which we have and continue to pcie_port_device_register().
> - Now ,the function pcie_port_device_register() will FAIL. It will fail because it will call assign_interrupt_mode(), return with PCIE_PORT_NO_IRQ, and giveup with a reasonable remark in the code
> "/*
> * Don't use service devices that require interrupts if there is
> * no way to generate them.
> */"
> 
> So now the question is why calling assign_interrupt_mode() with the P2020 PCIe ROOT device return empty? Well...
> - First assign_interrupt_mode() will test for PCIE_PORT_MSIX_MODE. Freescale PCIe does not support this...
> - Second attampt is made to discover PCIE_PORT_MSI_MODE, which Freescale should support but the PCIe PCI_CAP_ID_MSI capability is published on the device side of the bridge and NOT on the PCIe ROOT device, which is the one probed and thus fails.
> - Last it attempts to look at "dev->pin" in order to set PCIE_PORT_INTx_MODE. On top of being the less recommended way (the old way), The Freescale PCIE ROOT device pin is not set anywhere.
> 
> Failing all those the probe fails and the AER service is not activated for the PCIE device.
> 
> QUESTION:
> 1. What am I missing?
> 2. Has anyone enabled the AER PCIe service for P2020/MPC85xx?
> 3. Should the PCIe ROOT end report MSI capabilities or should the device end report itself as bridge ???
> 
> -- Liberty

Do you have some code that enables AER on P2020.  If so it might be easier to see what's going on.

- k