[PATCH v4] powerpc: Add hibernation support for FSL BookE processors

[Kumar Gala]

On Apr 16, 2010, at 2:03 PM, Anton Vorontsov wrote:

> This is started as swsusp_32.S modifications, but the amount of #ifdefs
> made the whole file horribly unreadable, so let's put the support into
> its own separate file.
> 
> The code should be relatively easy to modify to support 44x BookEs as
> well, but since I don't have any 44x to test, let's confine the code to
> FSL BookE. (The only FSL-specific part so far is 'flush_dcache_L1'.)
> 
> Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
> ---
> 
> On Fri, Apr 16, 2010 at 10:54:36AM -0500, Scott Wood wrote:
>> Anton Vorontsov wrote:
>>> +	/* Invalidate TLB0 & TLB1 */
>>> +	li	r6,0x04
>>> +	tlbivax 0,r6
>>> +	TLBSYNC
>>> +	li	r6,0x0c
>>> +	tlbivax 0,r6
>>> +	TLBSYNC
>> 
>> Is this needed?  Shouldn't the boot process have already given us a
>> sane TLB?
> 
> Thanks for catching, it seems that it's just a left over from
> some debugging code and not actually needed. ..that reminded me
> the time I spent inserting BookE specific code into swsusp_32.S,
> and then debugging all that #ifdef mess...
> 
> This is tested on e500v2.
> 
> arch/powerpc/kernel/Makefile       |    8 +-
> arch/powerpc/kernel/swsusp_booke.S |  192 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 198 insertions(+), 2 deletions(-)
> create mode 100644 arch/powerpc/kernel/swsusp_booke.S

Scott, you ok (ACK) this version or still need tweaks?

- k