[PATCHv3] [RFC] Xilinx Virtex 4 FX Soft FPU support

[Stephen Neuendorffer]

> -----Original Message-----
> From: linuxppc-dev-bounces+stephen=neuendorffer.name at lists.ozlabs.org [mailto:linuxppc-dev-
> bounces+stephen=neuendorffer.name at lists.ozlabs.org] On Behalf Of Grant Likely
> Sent: Wednesday, June 16, 2010 1:02 PM
> To: Sergey Temerkhanov
> Cc: linuxppc-dev at lists.ozlabs.org; John Linn
> Subject: Re: [PATCHv3] [RFC] Xilinx Virtex 4 FX Soft FPU support
> 
> On Wed, May 26, 2010 at 11:04 AM, Sergey Temerkhanov
> <temerkhanov at cifronik.ru> wrote:
> > This patch enables support for Xilinx Virtex 4 FX singe-float FPU.
> >
> > Changelog v2-v3:
> >        -Fixed whitespaces for SAVE_FPR/REST_FPR.
> >        -Changed description of MSR_AP bit.
> >        -Removed the stub for APU unavailable exception.
> >
> > Changelog v1->v2:
> >        -Added MSR_AP bit definition
> >        -Renamed CONFIG_XILINX_FPU to CONFIG_XILINX_SOFTFPU, moved it to
> >         'Platform support' and made it Virtex4-FX-only.
> >        -Changed SAVE_FPR/REST_FPR definition style.
> >
> > Caveats:
> >        - Hard-float binaries which rely on in-kernel math emulation will
> >        give wrong results since they expect 64-bit double-precision instead of
> >        32-bit single-precision numbers which Xilinx V4-FX Soft FPU produces.

Perhaps this caveat should go in the description of the configuration option?

Steve


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