[PATCH] PowerPC: Remove hardcoded BAT configuration of IMMR in CPM early debug console
Martyn Welch
martyn.welch at ge.com
Tue Jun 1 23:43:32 EST 2010
Martyn Welch wrote:
> Scott Wood wrote:
>
>> On 05/28/2010 10:18 AM, Martyn Welch wrote:
>>
>>> The CPM early debug console hardcodes the BAT to cover the IMMR at
>>> 0xf0000000. The IMMR (on the mpc8270 at the very least) can be set to a
>>> number of locations with bootstrap configuration, which are outside the
>>> hardcoded BAT configuration.
>>>
>>> This patch determines the correct location at which to configure a BAT
>>> during the boot process from the supplied PPC_EARLY_DEBUG_CPM_ADDR.
>>>
>>> Signed-off-by: Martyn Welch<martyn.welch at ge.com>
>>> ---
>>>
>>> arch/powerpc/kernel/head_32.S | 5 +++--
>>> arch/powerpc/sysdev/cpm_common.c | 4 +++-
>>> 2 files changed, 6 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/powerpc/kernel/head_32.S
>>> b/arch/powerpc/kernel/head_32.S
>>> index e025e89..861cace 100644
>>> --- a/arch/powerpc/kernel/head_32.S
>>> +++ b/arch/powerpc/kernel/head_32.S
>>> @@ -1194,12 +1194,13 @@ setup_disp_bat:
>>> #endif /* CONFIG_BOOTX_TEXT */
>>>
>>> #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
>>> +#define PPC_EARLY_DEBUG_CPM_ADDR
>>> ASM_CONST(CONFIG_PPC_EARLY_DEBUG_CPM_ADDR)
>>> setup_cpm_bat:
>>> - lis r8, 0xf000
>>> + lis r8, PPC_EARLY_DEBUG_CPM_ADDR at ha
>>> ori r8, r8, 0x002a
>>> mtspr SPRN_DBAT1L, r8
>>>
>>> - lis r11, 0xf000
>>> + lis r11, PPC_EARLY_DEBUG_CPM_ADDR at ha
>>> ori r11, r11, (BL_1M << 2) | 2
>>> mtspr SPRN_DBAT1U, r11
>>>
>> Only the physical address should depend on where IMMR is. We should
>> use fixmap instead of an arbitrary address for the effective address.
>> There's a existing FIX_EARLY_DEBUG_BASE, but it's only 128 KiB so
>> we'll have to either grow it, or map only a subset of IMMR.
>>
>>
>
> I think that's a more fundamental change to CPM early debug than I can
> handle right now.
>
>
>> Plus, CONFIG_PPC_EARLY_DEBUG_CPM_ADDR points to the TX descriptor, not
>> to the beginning of IMMR, so you should mask off the lower 20 bits
>> (the offset is probably less than 64K, and the BAT might just ignore
>> the extra bits anyway, but why take chances?).
>>
>>
>
> I assume that an extra instruction "andi r8, r8, 0xfff0" after each
> "lis" instruction would be what you are looking for?
>
>
"andis" even.
Martyn
> Martyn
>
>
>> -Scott
>>
>
>
>
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748 | Barbirolli Square, Manchester,
E martyn.welch at ge.com | M2 3AB VAT:GB 927559189
More information about the Linuxppc-dev
mailing list