[PATCH v2 1/2] DTS: Change deprecated binding for 85xx-based boards

[Bradley Hughes]

The "fsl,85..." style compatible binding was to be deprecated
some time ago.  This patch corrects existing occurrences of
the incorrect binding.  The memory-controller and
l2-cache-controller are the only affected nodes.

Signed-off-by: Bradley Hughes <bhughes at silicontkx.com>
---
 arch/powerpc/boot/dts/mpc8540ads.dts |    4 ++--
 arch/powerpc/boot/dts/mpc8541cds.dts |    4 ++--
 arch/powerpc/boot/dts/mpc8544ds.dts  |    4 ++--
 arch/powerpc/boot/dts/mpc8548cds.dts |    4 ++--
 arch/powerpc/boot/dts/mpc8555cds.dts |    4 ++--
 arch/powerpc/boot/dts/mpc8560ads.dts |    4 ++--
 arch/powerpc/boot/dts/mpc8568mds.dts |    4 ++--
 7 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts
b/arch/powerpc/boot/dts/mpc8540ads.dts
index 9dc2929..8d1bf0f 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -71,14 +71,14 @@
 		};

 		memory-controller at 2000 {
-			compatible = "fsl,8540-memory-controller";
+			compatible = "fsl,mpc8540-memory-controller";
 			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
 			interrupts = <18 2>;
 		};

 		L2: l2-cache-controller at 20000 {
-			compatible = "fsl,8540-l2-cache-controller";
+			compatible = "fsl,mpc8540-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
 			cache-size = <0x40000>;	// L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts
b/arch/powerpc/boot/dts/mpc8541cds.dts
index 9a3ad31..87ff965 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -71,14 +71,14 @@
 		};

 		memory-controller at 2000 {
-			compatible = "fsl,8541-memory-controller";
+			compatible = "fsl,mpc8541-memory-controller";
 			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
 			interrupts = <18 2>;
 		};

 		L2: l2-cache-controller at 20000 {
-			compatible = "fsl,8541-l2-cache-controller";
+			compatible = "fsl,mpc8541-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
 			cache-size = <0x40000>;	// L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts
b/arch/powerpc/boot/dts/mpc8544ds.dts
index 98e94b4..d793968 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -73,14 +73,14 @@
 		};

 		memory-controller at 2000 {
-			compatible = "fsl,8544-memory-controller";
+			compatible = "fsl,mpc8544-memory-controller";
 			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
 			interrupts = <18 2>;
 		};

 		L2: l2-cache-controller at 20000 {
-			compatible = "fsl,8544-l2-cache-controller";
+			compatible = "fsl,mpc8544-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
 			cache-size = <0x40000>;	// L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts
b/arch/powerpc/boot/dts/mpc8548cds.dts
index 0f52624..a17a557 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -74,14 +74,14 @@
 		};

 		memory-controller at 2000 {
-			compatible = "fsl,8548-memory-controller";
+			compatible = "fsl,mpc8548-memory-controller";
 			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
 			interrupts = <18 2>;
 		};

 		L2: l2-cache-controller at 20000 {
-			compatible = "fsl,8548-l2-cache-controller";
+			compatible = "fsl,mpc8548-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
 			cache-size = <0x80000>;	// L2, 512K
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts
b/arch/powerpc/boot/dts/mpc8555cds.dts
index 065b2f0..5c5614f 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -71,14 +71,14 @@
 		};

 		memory-controller at 2000 {
-			compatible = "fsl,8555-memory-controller";
+			compatible = "fsl,mpc8555-memory-controller";
 			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
 			interrupts = <18 2>;
 		};

 		L2: l2-cache-controller at 20000 {
-			compatible = "fsl,8555-l2-cache-controller";
+			compatible = "fsl,mpc8555-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
 			cache-size = <0x40000>;	// L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts
b/arch/powerpc/boot/dts/mpc8560ads.dts
index a5bb1ec..6e85e1b 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -71,14 +71,14 @@
 		};

 		memory-controller at 2000 {
-			compatible = "fsl,8540-memory-controller";
+			compatible = "fsl,mpc8540-memory-controller";
 			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
 			interrupts = <18 2>;
 		};

 		L2: l2-cache-controller at 20000 {
-			compatible = "fsl,8540-l2-cache-controller";
+			compatible = "fsl,mpc8540-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
 			cache-size = <0x40000>;	// L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts
b/arch/powerpc/boot/dts/mpc8568mds.dts
index 92fb178..30cf0e0 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -124,14 +124,14 @@
 		};

 		memory-controller at 2000 {
-			compatible = "fsl,8568-memory-controller";
+			compatible = "fsl,mpc8568-memory-controller";
 			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
 			interrupts = <18 2>;
 		};

 		L2: l2-cache-controller at 20000 {
-			compatible = "fsl,8568-l2-cache-controller";
+			compatible = "fsl,mpc8568-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
 			cache-size = <0x80000>;	// L2, 512K
-- 
1.7.0.4