[PATCH] DTS: Adding device tree source for the STx GP3 SSA MPC8555-based board.

Bradley Hughes bhughes at silicontkx.com
Thu Jul 22 02:52:52 EST 2010


On Wed, Jul 21, 2010 at 10:24 AM, Kumar Gala <galak at kernel.crashing.org> wrote:
>>
>> +     soc8555 at e0000000 {
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +             device_type = "soc";
>> +             compatible = "simple-bus";
>> +             ranges = <0x0 0xe0000000 0x100000>;
>> +             bus-frequency = <0>;
>> +
>> +             ecm-law at 0 {
>> +                     compatible = "fsl,ecm-law";
>> +                     reg = <0x0 0x1000>;
>> +                     fsl,num-laws = <8>;
>> +             };
>> +
>> +             ecm at 1000 {
>> +                     compatible = "fsl,mpc8555-ecm", "fsl,ecm";
>> +                     reg = <0x1000 0x1000>;
>> +                     interrupts = <17 2>;
>> +                     interrupt-parent = <&mpic>;
>> +             };
>> +
>> +             memory-controller at 2000 {
>> +                     compatible = "fsl,8555-memory-controller";
>
> fsl,mpc8555?

Ah, yes -- it seems the dts I used for an example also has this
problem.  In drivers/edac/mpc85xx_edac.c, bindings still work for
fsl,85.. style notation, but a comment claims that this notation would
be deprecated at some point (2.6.29 or 2.6.30).  I have updated my
local copy and it works fine, should I send a new patch?  I could also
extend this change to the other DTS files affected (A quick search
found 14 instances of fsl,85.. style notation.)  Please let me know
what I should do.

>
>> +                     reg = <0x2000 0x1000>;
>> +                     interrupt-parent = <&mpic>;
>> +                     interrupts = <18 2>;
>> +             };
>> +
>> +             L2: l2-cache-controller at 20000 {
>
> fsl,mpc8555?
>
>> +                     compatible = "fsl,8555-l2-cache-controller";
>> +                     reg = <0x20000 0x1000>;
>> +                     cache-line-size = <32>; // 32 bytes
>> +                     cache-size = <0x40000>; // L2, 256K
>> +                     interrupt-parent = <&mpic>;
>> +                     interrupts = <16 2>;
>> +             };
>> +
>
> - k
>
>
>
>

Best Regards,
Bradley


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