MPC831x (and others?) NAND erase performance improvements

[Joakim Tjernlund]

Scott Wood <scottwood at freescale.com> wrote on 2010/12/13 20:49:50:
>
> On Mon, 13 Dec 2010 20:30:27 +0100
> Joakim Tjernlund <joakim.tjernlund at transmode.se> wrote:
>
> > Scott Wood <scottwood at freescale.com> wrote on 2010/12/13 18:51:31:
> > >
> > > On Mon, 13 Dec 2010 18:41:32 +0100
> > > Joakim Tjernlund <joakim.tjernlund at transmode.se> wrote:
> > >
> > > > Scott Wood <scottwood at freescale.com> wrote on 2010/12/13 18:33:56:
> > > > >
> > > > > On Mon, 13 Dec 2010 11:32:00 +0100
> > > > > Joakim Tjernlund <joakim.tjernlund at transmode.se> wrote:
> > > > >
> > > > > > What if one has several NAND chips to build a big FS? Is the NAND
> > > > > > controller equipped to handle that?
> > > > >
> > > > > FCM can drive one NAND chip per eLBC chipselect, though possibly you
> > > > > could go beyond that with a board-logic chipselect mechanism.
> > > >
> > > > hmm, then I guess one would have to use one GPIO/IRQ per NAND chip?
> > >
> > > Couldn't you just tie together all the open-drain busy lines before you
> > > invert it?  You'll only be driving one NAND chip at a time anyway; the
> > > others should not be asserting busy.
> >
> > hmm, I guess that would work(didn't know they were open-drain), thanks.
> > Is that how the FCM do it?
>
> Yes, that's what started this discussion. :-)

True, I must be getting old :)

>
> The problem there is that they share the line with all chipselects,
> NAND or otherwise.

Right, thanks for reminding me.