[PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite
joakim.tjernlund at transmode.se
Sat Oct 3 21:47:45 EST 2009
Benjamin Herrenschmidt <benh at kernel.crashing.org> wrote on 03/10/2009 12:57:28:
> On Sat, 2009-10-03 at 11:24 +0200, Joakim Tjernlund wrote:
> > So yes, there is a missing _tlbil_va() missing for 8xx somewhere
> > but there is something more too.
> > Maybe your new filter functions and my
> > powerpc, 8xx: DTLB Error must check for more errors.
> > will do the trick?
> Well, if we can't tell between a load and a store on a TLB miss, then
> we should probably let it create an unpopulated entry in all cases,
> so that we do take a proper DSI/ISI the second time around, which
> would then tell us where we come from...
Not quite sure what you mean here?
Always branch to DSI at TLB Miss and create a unpopulated
entry? That does not feel right.
The current method is better. The only odd thing is
the null pmd entry and what to load into RPN. I am not convinced
that it is a problem but I would like to see a generic impl. of
a null pmd and use that instead. A 8xx impl. of that
looks like this(tested on 2.4, works fine)
lwz r11, 0(r10) /* Get the level 1 entry */
rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
bne+ 4f /* If zero, use a null pmd */
lis r11, null_pmd_dir at h
ori r11, r11, null_pmd_dir at l
If the pmd_none() and friends are updated to test for a null_pmd_dir
we can loose the test above and save 4 insn :)
Anyhow did you post a patch(can't find one) about your suggested
filter functions for 8xx? I sure would like to see one :)
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