[RFC PATCH 03/19] powerpc: gamecube: bootwrapper bits

[Gabriel Paubert]

On Thu, Nov 26, 2009 at 03:36:56PM +1100, Benjamin Herrenschmidt wrote:
> On Tue, 2009-11-24 at 22:00 +0100, Segher Boessenkool wrote:
> > 
> > Sure, the memory controllers don't do coherency.  I'm slightly worried
> > about two things:
> > 1) Will the generic code use M=0 as well?  Is it a problem if it  
> > doesn't?
> 
> We can make it not do it.
> 
> > 2) Do lwarx. etc. work in M=0? 
> 
> They should hopefully... as long as you don't rely on the reservation
> blowing as a result of a DMA write.

Hmm, this really depends on whether the DMA transfers generate bus cycles
that require coherency or not. Not the other way around. M=1 only forces
bus cycles to be snooped by other processors (asserting the GBL signal
on 603/604/750 busses).

The host bridge is free to systematically snoop processor accesses (to make 
sure that data queued in the bridge and not yet written to memory is seen
in the coherent memory domain even if, for example, interrupts propagate 
so fast that DMA target addresses are accessed before it is written to RAM).

On memory coherent systems, the host bridge has to assert the GBL signal,
to force data to be written to memory (for most DMA accesses), or to  
invalidate caches (for full line writes from devices).

	Gabriel