spi_mpc8xxx.c: chip select polarity problem
Grant Likely
grant.likely at secretlab.ca
Thu Nov 26 09:11:57 EST 2009
On Wed, Nov 25, 2009 at 1:41 PM, Torsten Fleischer
<to-fleischer at t-online.de> wrote:
> On Wen, Nov 25, 2009 at 01:33:57 Grant Likely wrote:
>> Thanks. However, there needs to be a proper description of what this
>> patch does to go in the commit header. Can you please write one?
>>
>> Thanks,
>> g.
>>
> [...]
>
> The initialization of the chip selects is removed from the probe() function of
> the spi_mpc8xxx driver, because the driver doesn't know the polarity of the
> chip selects of the SPI devices at the time of its initialization.
>
> For this reason the initialization of the several chip selects is postponed
> to the point of time when the very first SPI transfer to the associated device
> occurs.
>
>
> Signed-off-by: Torsten Fleischer <to-fleischer at t-online.de>
Ah. I understand what you're doing now. Hmmm. This approach
concerns me because it relies on firmware or platform code to get CS
gpios set up properly before the driver is probed. Firmware doesn't
always get it right, and I prefer to avoid platform specific setups as
much as possible. Why can't the CS polarity be encoded into the
device tree so the driver *does* have the polarity data at probe time?
g.
> ---
>
> diff -u -r -N linux-2.6.31.6_orig//drivers/spi/spi_mpc8xxx.c linux-2.6.31.6/drivers/spi/spi_mpc8xxx.c
> --- linux-2.6.31.6_orig//drivers/spi/spi_mpc8xxx.c 2009-11-10 01:32:31.000000000 +0100
> +++ linux-2.6.31.6/drivers/spi/spi_mpc8xxx.c 2009-11-19 08:15:33.000000000 +0100
> @@ -114,6 +114,7 @@
> u32 rx_shift; /* RX data reg shift when in qe mode */
> u32 tx_shift; /* TX data reg shift when in qe mode */
> u32 hw_mode; /* Holds HW mode register settings */
> + int initialized;
> };
>
> static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
> @@ -503,15 +504,52 @@
>
> return ret;
> }
> +
> +
> +struct mpc8xxx_spi_probe_info {
> + struct fsl_spi_platform_data pdata;
> + int *gpios;
> + bool *alow_flags;
> +};
> +
> +static struct mpc8xxx_spi_probe_info *
> +to_of_pinfo(struct fsl_spi_platform_data *pdata)
> +{
> + return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
> +}
> +
> +static int mpc8xxx_spi_cs_init(struct spi_device *spi)
> +{
> + struct device *dev = spi->dev.parent;
> + struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
> + u16 cs = spi->chip_select;
> + int gpio = pinfo->gpios[cs];
> + bool on = pinfo->alow_flags[cs] ^ !(spi->mode & SPI_CS_HIGH);
> +
> + return gpio_direction_output(gpio, on);
> +}
> +
> static int mpc8xxx_spi_transfer(struct spi_device *spi,
> struct spi_message *m)
> {
> struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
> + struct spi_mpc8xxx_cs *cs = spi->controller_state;
> unsigned long flags;
>
> m->actual_length = 0;
> m->status = -EINPROGRESS;
>
> + if (cs && !cs->initialized) {
> + int ret;
> +
> + ret = mpc8xxx_spi_cs_init(spi);
> + if (ret) {
> + dev_dbg(&spi->dev, "cs_init failed: %d\n", ret);
> + return ret;
> + }
> + cs->initialized = 1;
> + }
> +
> spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
> list_add_tail(&m->queue, &mpc8xxx_spi->queue);
> queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
> @@ -648,18 +686,6 @@
> return 0;
> }
>
> -struct mpc8xxx_spi_probe_info {
> - struct fsl_spi_platform_data pdata;
> - int *gpios;
> - bool *alow_flags;
> -};
> -
> -static struct mpc8xxx_spi_probe_info *
> -to_of_pinfo(struct fsl_spi_platform_data *pdata)
> -{
> - return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
> -}
> -
> static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
> {
> struct device *dev = spi->dev.parent;
> @@ -720,14 +746,6 @@
>
> pinfo->gpios[i] = gpio;
> pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
> -
> - ret = gpio_direction_output(pinfo->gpios[i],
> - pinfo->alow_flags[i]);
> - if (ret) {
> - dev_err(dev, "can't set output direction for gpio "
> - "#%d: %d\n", i, ret);
> - goto err_loop;
> - }
> }
>
> pdata->max_chipselect = ngpios;
>
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
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