[PATCH 0/8] 8xx: Misc fixes for buggy insn

[Joakim Tjernlund]

Scott Wood <scottwood at freescale.com> wrote on 10/11/2009 17:55:28:
>
> Scott Wood wrote:
> > Joakim Tjernlund wrote:
> >> Why does not pinning interact well with CPU15? If pinned, you never get
> >> a TLB miss for kernel text so that should mitigate the CPU15 problem.
> >
> > The nature of the workaround for CPU15 is that we can't keep it pinned
> > -- we have to take an ITLB miss on every page boundary crossing.  If you
> > try to pin, it'll just be invalidated by the workaround.
>
> Except that the invalidation only happens when you take an ITLB miss on
> an adjacent page, which means we'd likely never get CPU15 protection for
> kernel code if pinning is enabled. :-(

So tlbie invalidates pinned TLBs too?
It is likely that you won't get ITLB Misses for normal kernel
space but for modules you will. Also, since the pinned D&I TLBs overlap,
how do you make sure that invalidating a kernel DTLB won't
spill over to the pinned ITLB?

Does pinned TLBs work for you?
Rex, how does it look in your end?

 Jocke