Weird 5200/mtd-ram problem

[Gary Thomas]

Albrecht Dreß wrote:
> Am 20.05.09 16:23 schrieb(en) Gary Thomas:
>> > In Linux, when I write the file to /dev/mtdx, the last dword of each
>> block is broken, e.g. when running "dd if=pattern of=/dev/mtd5 bs=512"
>> the dword's at offset 0x1fc, 0x3fc, ... are 0x0000aaaa (instead of
>> 0x0055aaff), if I use bs=1024 the dwords at 0x3fc, 0x7fc, ... show
>> this value, if I use bs=4096 the dword at 0xffc shows this value,
>> etc.  I looked at the CS/WR lines with a scope, and I couldn't see
>> anything special.  The timing should be fine, as u-boot uses the same
>> as Linux.
>> >
>> > Any idea what goes wrong here?  I guessed I missed something in the
>> LPB setup...
>>
>> Check your cache setup - the BDI is most certainly not accessing this
>> via the Data cache whereas Linux probably will be.
> 
> Hmm, yes - I didn't touch the vanilla Lite5200B Linux setup there, which
> has a flash chip at cs1...
> 
> If it is really a cache problem (I'm away now from my test board) -
> isn't a sync sufficient after doing the copy to the external ram
> (lpb/cs1)?  What is the proper approach for devices attached to the
> localbus?

Based on the behaviour, it's probably a timing problem with
multi-beat transfers.  When the PowerPC does cache flushes,
the chip activity is very different than the single beat accesses
used by the BDI.

Try to access this without using the cache.  If it works properly
then you'll need to look at the timing setup (the local bus registers)
to see why it fails with the multi-beat accesses.

-- 
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Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
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