[PATCH] ucc_geth: Rework the TX logic.

[Li Yang]

On Tue, Mar 31, 2009 at 5:07 PM, Joakim Tjernlund
<Joakim.Tjernlund at transmode.se> wrote:
> Scott Wood <scottwood at freescale.com> wrote on 30/03/2009 21:32:23:
>>
>> Joakim Tjernlund wrote:
>> >> different since descriptors are in MURAM which is ioremap()ed --
> though
>> >> switching to a cacheable mapping with barriers should be a
> performance
>> >> improvement.
>> >
>> > I always thought that MURAM was very fast. The whole reason to have
> BDs in
>> > MURAM is that it is faster than normal RAM, at least that is what I
>> > thought.
>>
>> Yeah, on second thought it probably wouldn't be worth it.  There's also
>> the question of under what circumstances the QE's MURAM accesses will be
>
>> cache-coherent.
>
> I am a bit confused, what isn't worth it? Currently MURAM isn't used by
> ucc_geth, but
> it is easy to change. Swap MEM_PART_SYSTEM to MEM_PART_MURAM, however,
> just
> tried that and the driver stopped working. I known this worked earlier
> because
> I tried it and I even think I sent a patch to Leo.
>
> What choices do we have, I see three:
>
> 1) MEM_PART_SYSTEM, as today.
> 2) MEM_PART_MURAM. I guess this should be uncacheable memory?
> 3) as gianfar, dma_alloc_coherent(). I presume this is uncacheable memory?
>

1 and 3 are the same.  All of them use cacheable memory as we have a
hardware coherency module to take care of the cache coherency problem.
 However it might be better to use dma_alloc_coherent() for the code
to be more readible.  Thanks.

- Leo