PCIe interrupts in the device tree

[Kumar Gala]

On Mar 24, 2009, at 4:13 PM, Johns Daniel wrote:

>
> On Tue, Mar 24, 2009 at 3:54 PM, Kumar Gala  
> <galak at kernel.crashing.org> wrote:
>
> On Mar 24, 2009, at 3:24 PM, Johns Daniel wrote:
>
> Could somebody please explain the declaration of the PCIe interrupts
> in the device tree?
>
> I was under the impression that PCIe interrupts in the PowerPC Linux
> kernel default to using INTx signaling (vs. external IRQ pin assertion
> and MSI signaling). Am I right?
>
> If so, then do the interrupt-map lines in the DTS refer to the
> internal IRQ used by Freescale processors to implement INTx virtual
> wire interrupts?
>
> For example, in the mpc8536ds.dts file, under "pci1: pcie at ffe09000"  
> we have:
>                interrupt-map = <
>                        /* IDSEL 0x0 */
>                        0000 0 0 1 &mpic 4 1
>                        0000 0 0 2 &mpic 5 1
>                        0000 0 0 3 &mpic 6 1
>                        0000 0 0 4 &mpic 7 1
>                        >;
> Are the 4, 5, 6, and 7 internal or external IRQs?
>
> The .dts and linux make no distinction between internal & external  
> IRQs.  This is a silly artifact of Freescale UMs.  IRQ 0 starts at  
> offset 0x50000 and each 0x20 offset is another IRQ.  So typically  
> External 0 == IRQ0, Internal 0 == IRQ16.
>
> So this says that Ext 4, 5, 6, 7 and wired to INTA, INTB, INTC, INTD  
> for this particular PCIe controller.
>
> When you say "wired", do you mean hard-wired?

Yes.  The INTx emulation interrupts are hard-wired by the SoC on top  
of the external IRQs.

> If so, how would you specify and use INTx message interrupts?

Do you mean MSI or INTx emulation?

- k