[RFC][PATCH v4] powerpc/mm: e300c2/c3/c4 TLB errata workaround

[David Jander]

Ok, I was analysing your code (which seems much more compact than mine):

On Monday 16 March 2009 14:02:18 Kumar Gala wrote:
>[...]
> --- a/arch/powerpc/kernel/head_32.S
> +++ b/arch/powerpc/kernel/head_32.S
> @@ -587,9 +587,19 @@ DataLoadTLBMiss:
>  	ori	r1,r1,0xe04		/* clear out reserved bits */
>  	andc	r1,r0,r1		/* PP = user? (rw&dirty? 2: 3): 0 */
>  	mtspr	SPRN_RPA,r1
> +	mfspr	r2,SPRN_SRR1		/* Need to restore CR0 */
> +	mtcrf	0x80,r2
> +BEGIN_MMU_FTR_SECTION
> +	li	r0,1
> +	lwz	r1,sw_way_lru at l(0)
> +	rlwinm	r3,r3,19,25,29		/* Get Address bits 19:15 */

This should be 'rlwinm	r3,r3,17,27,31' now, since you address bits, not ints.
Note that you are trashing r3 (SPRN_DMISS) here!

> +	slw	r0,r0,r3
> +	xor	r1,r0,r1
> +	srw	r0,r1,r3
> +	stw	r1,sw_way_lru at l(0)
> +	rlwimi	r2,r0,31-14,14,14
> +END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
>  	tlbld	r3

And now you load r3 into the tlb, is this right? It doesn't seem right to 
me....

> -	mfspr	r3,SPRN_SRR1		/* Need to restore CR0 */
> -	mtcrf	0x80,r3
>  	rfi
>  DataAddressInvalid:
>  	mfspr	r3,SPRN_SRR1
> @@ -652,11 +662,25 @@ DataStoreTLBMiss:
>  	li	r1,0xe05		/* clear out reserved bits & PP lsb */
>  	andc	r1,r0,r1		/* PP = user? 2: 0 */
>  	mtspr	SPRN_RPA,r1
> +	mfspr	r2,SPRN_SRR1		/* Need to restore CR0 */
> +	mtcrf	0x80,r2
> +BEGIN_MMU_FTR_SECTION
> +	li	r0,1
> +	lwz	r1,sw_way_lru at l(0)
> +	rlwinm	r3,r3,19,25,29		/* Get Address bits 19:15 */
> +	slw	r0,r0,r3
> +	xor	r1,r0,r1
> +	srw	r0,r1,r3
> +	stw	r1,sw_way_lru at l(0)
> +	rlwimi	r2,r0,31-14,14,14
> +END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
>  	tlbld	r3

Same thing here, r3 is trashed.

> -	mfspr	r3,SPRN_SRR1		/* Need to restore CR0 */
> -	mtcrf	0x80,r3
>  	rfi
>
> +	.balign	L1_CACHE_BYTES
> +sw_way_lru:
> +	.long 0
> +

Ok, I'll try to do it like this, but with lru stored in SPRG6

Best regards,

-- 
David Jander
Protonic Holland.