[RFC] [PATCH v2] MPC5121 TLB errata workaround

[Kumar Gala]

>

What does cat /proc/cpuinfo show on this board?

> +#ifdef CONFIG_PPC_MPC512x
> +/* MPC512x: workaround for errata in die M36P and earlier:
> + * Implement LRW for TLB way.
> + */

This errata impacts a number of cores and so we should make this a CPU  
feature fixup rather than #ifdef code.

> +       mfspr   r3,SPRN_DMISS
> +       rlwinm  r3,r3,19,25,29 /* Get Address bits 19:15 */
> +       lis     r2,lrw at ha       /* Search index in lrw[] */
> +       addi    r2,r2,lrw at l
> +       tophys(r2,r2)
> +       lwzx    r1,r3,r2       /* Get item from lrw[] */
> +       cmpwi   0,r1,0         /* Was it way 0 last time? */

Why not use a bit vector since we only need one bit of information.   
Additionally we can use a single SPRG at that point instead to keep  
track of the LRU information.

> +       beq-    0,113f         /* Then goto 113: */
> +
> +       mfspr   r1,SPRN_SRR1
> +       rlwinm  r1,r1,0,15,13  /* Mask out SRR1[WAY] */
> +       mtspr   SPRN_SRR1,r1
> +
> +       li      r0,0
> +       stwx    r0,r3,r2       /* Make lrw[] entry 0 */
> +       b       114f
> +113:
> +       li      r0,1
> +       stwx    r0,r3,r2       /* Make lrw[] entry 1 */
> +114:
> +#endif
>        mfctr   r0
>        /* Get PTE (linux-style) and check access */
>        mfspr   r3,SPRN_DMISS
> @@ -688,6 +717,34 @@ DataStoreTLBMiss:
>        .globl mol_trampoline
>        .set mol_trampoline, i0x2f00
>
> +#ifdef CONFIG_PPC_MPC512x
> +TlbWo:
> +/* MPC512x: workaround for errata in die M36P and earlier:
> + * Implement LRW for TLB way.
> + */
> +       mfspr   r3,SPRN_DMISS
> +       rlwinm  r3,r3,19,25,29 /* Get Address bits 19:15 */
> +       lis     r2,lrw at ha       /* Search index in lrw[] */
> +       addi    r2,r2,lrw at l
> +       tophys(r2,r2)
> +       lwzx    r1,r3,r2       /* Get item from lrw[] */
> +       cmpwi   0,r1,0         /* Was it way 0 last time? */
> +       beq-    0,113f         /* Then goto 113: */
> +
> +       mfspr   r1,SPRN_SRR1
> +       rlwinm  r1,r1,0,15,13  /* Mask out SRR1[WAY] */
> +       mtspr   SPRN_SRR1,r1
> +
> +       li      r0,0
> +       stwx    r0,r3,r2       /* Make lrw[] entry 0 */
> +       b       114f
> +113:
> +       li      r0,1
> +       stwx    r0,r3,r2       /* Make lrw[] entry 1 */
> +114:
> +       b       RFTlbWo
> +#endif
> +
>        . = 0x3000
>
> AltiVecUnavailable:
> @@ -1321,6 +1378,14 @@ intercept_table:
>        .long 0, 0, 0, 0, 0, 0, 0, 0
>        .long 0, 0, 0, 0, 0, 0, 0, 0
>        .long 0, 0, 0, 0, 0, 0, 0, 0
> +
> +#ifdef CONFIG_PPC_MPC512x
> +lrw:
> +       .long 0, 0, 0, 0, 0, 0, 0, 0
> +       .long 0, 0, 0, 0, 0, 0, 0, 0
> +       .long 0, 0, 0, 0, 0, 0, 0, 0
> +       .long 0, 0, 0, 0, 0, 0, 0, 0
> +#endif
>
> /* Room for two PTE pointers, usually the kernel and current user  
> pointers
>  * to their respective root page table.
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