[PATCH] Add unwind information for SPE registers of E500 core

[Kumar Gala]

On Mar 3, 2009, at 10:51 PM, Liming Wang wrote:

> SPE registers use the high part bit0~bit31 of E500 GPR0~GPR31.
> The unwind information in "eh_frame" section is used during exception
> handling and describes register information in the signal frame. But
> current unwind information doesn't cover SPE registers, which have
> been saved in the signal frame. This patch adds this unwind  
> information
> to "eh_frame" section.
>
> SPE registers use register number 1200+N to identify register 'N', but
> they start from 113 in unwind column, which is computed from gcc
> source code, macro DWARF_REG_TO_UNWIND_COLUMN:
>
> 	#define FIRST_PSEUDO_REGISTER 114
> 	#define DWARF_REG_TO_UNWIND_COLUMN(r) \
>  	  ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
>
> Signed-off-by: Liming Wang <liming.wang at windriver.com>
> ---
> arch/powerpc/kernel/vdso32/sigtramp.S |   34 ++++++++++++++++++++++++ 
> +++++++++
> 1 files changed, 34 insertions(+), 0 deletions(-)

What about SPEFSCR & the accumulator?  Are they not part of the  
frame?  They probably should be.

> diff --git a/arch/powerpc/kernel/vdso32/sigtramp.S b/arch/powerpc/ 
> kernel/vdso32/sigtramp.S
> index 68d49dd..789a343 100644
> --- a/arch/powerpc/kernel/vdso32/sigtramp.S
> +++ b/arch/powerpc/kernel/vdso32/sigtramp.S
> @@ -251,6 +251,40 @@ V_FUNCTION_END(__kernel_sigtramp_rt32)
>   vsave_msr1 (31);							\
>   vsave_msr2 (33, 32*16+12);						\
>   vsave      (32, 32*16)
> +#elif defined(CONFIG_SPE)
> +#define EH_FRAME_VMX \

introduce EH_FRAME_SPE.

> +  rsave (113, VREGS);							\

we should probably be doing the same thing as vsave_msr1()

- k