[RFC][PATCH v5] MPC5121 TLB errata workaround

[Kumar Gala]

On Jun 6, 2009, at 5:42 PM, Benjamin Herrenschmidt wrote:

> On Sun, 2009-06-07 at 00:07 +0200, Wolfgang Denk wrote:
>> Dear David Jander,
>>
>> In message <200903161652.09747.david.jander at protonic.nl> you wrote:
>>> Complete workaround for DTLB errata in e300c2/c3/c4 processors.
>>>
>>> Due to the bug, the hardware-implemented LRU algorythm always goes  
>>> to way
>>> 1 of the TLB. This fix implements the proposed software workaround  
>>> in
>>> form of a LRW table for chosing the TLB-way.
>>>
>>> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
>>> Signed-off-by: David Jander <david at protonic.nl>
>>
>> What is the actual status of this patch?
>>
>> Patchwork (http://patchwork.ozlabs.org/patch/24502/) says it's
>> "superseded" - but by what?
>>
>> I can't see such code in mainline - what happened to it?
>
> I can see the code in mainline ... but only in the -data- TLB miss
> handler, not the instruction one...
>
> Kumar ? Shouldn't we have the workaround in both ?

The errata was only for the d-side.  The patch is in the mainline  
kernel.

- k