[PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards

[Kumar Gala]

On Feb 10, 2009, at 9:10 AM, Anton Vorontsov wrote:

> commit e85477f516c2de7ed515fcf94ceab5282eba7fa4 ("powerpc/83xx: Fix
> TSEC0 workability on MPC8313E-RDB boards") fixed TSEC0 workability for
> rev. A and rev. B boards by using fixed-link property for VSC 7385
> 5-port switch. But rev. C boards have an option where TSEC0 connected
> to a Marvell PHY, which is a normal PHY on MDIO bus.
>
> So far U-Boot does not fix up TSEC0 nodes for MPC8313E-RDB boards, so
> we'd better include two device-tree files: one that specify Vitesse
> PHY and another for boards with Marvell PHY option.
>
> Reported-by: Li Yang <leoli at freescale.com>
> Signed-off-by: Anton Vorontsov <avorontsov at ru.mvista.com>
> ---
>
> Li, thanks for heads-up!
>
> One thing though: documentation says that Marvell PHY address is
> 0x3, while old device tree and this patch:
>
> http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add-default-dts.patch
>
> says "0x1"... I don't have any rev. C boards, so it would
> be great if somebody could confirm that 0x1 is the actual address.
>
> arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts |  401 ++++++++++++ 
> +++++++++
> arch/powerpc/configs/83xx/mpc8313_rdb_defconfig   |    2 +-
> 2 files changed, 402 insertions(+), 1 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts

did we decide that we don't have any bcsr or something that convey  
board rev or this setting?

- k