I2C bus clock on MPC85XX systems

Wolfgang Grandegger wg at grandegger.com
Wed Dec 23 05:40:01 EST 2009

Felix Radensky wrote:
> Hi, Wolfgang
> Wolfgang Grandegger wrote:
>> Felix Radensky wrote:
>>> Hi,
>>> Almost all MPC85XX based systems have the compatible=:"fsl-i2c" in
>>> respective
>>> i2c device tree nodes. This causes FSL i2c driver to use the following
>>> "backward
>>> compatible" values: FSR=0x31 DFSR=0x10. This is regardless of CCB clock
>>> frequency and i2c clock prescaler.
>>> On my custom MPC8536 based board with 432MHz CCB clock this results in
>>> 65KHz i2c clock frequency (checked with scope). U-Boot correctly
>>> configures
>>> the clock to 400KHz.
>>> I've fixed the problem by modifying device tree to use different
>>> compatible value,
>>> similar to what socrates board does. Is this the right approach ?
>> Are you aware of the properties described in
>> "Documentation/powerpc/dts-bindings/fsl/i2c.txt":
>> http://lxr.linux.no/#linux+v2.6.32/Documentation/powerpc/dts-bindings/fsl/i2c.txt
>> Wolfgang.
> Sure, I'm aware of these properties. I've used
> compatible = "fsl,mpc8543-i2c", "fsl-i2c";
> clock-frequency = <400000>;
> for my custom board.
> I think, however, that device trees for FSL reference designs should use
> them as well, to avoid setting i2c
> clock to some strange values. I may be wrong, but I think most custom

The FSR=0x31 DFSR=0x10 are not strange values. They have been used in
mainline kernels (< 2.6.30) for a long time.

> board developers borrow from
> reference device trees, so having a sane starting point would help.

The trees provided by Freescale are usually based on older kernel
version. Borrow from such trees is OK, but the project developers should
use a recent kernel version for development.


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