MPC5200B XLB Configuration Issues, FEC RFIFO Events, ATA Crashes

Roman Fietze roman.fietze at
Thu Dec 10 01:29:13 EST 2009


I had a discussion with some Freescale support people about the
constant RFIFO Event errors or PATA hard disk crashes when stressing a
board with (very) high loads, in my case even with some additional
traffic from an FPGA (or just the FLASH) via the SCLPC FIFO using the

The latest recommendation from Freescale was to set BSDIS and PLDIS
and to clear SE, resulting in a XLB config register value of
0x80012006, at least for my MPC5200B PVR/SVR of
0x80822014/0x80110022. If I am correct, the current XLB config setting
using the current U-Boot and kernel is 0x0000a006.

In order to get cache coherency I had to set
CONFIG_NOT_COHERENT_CACHE=y for the MPC5200B boards. Please correct me
if I am wrong with this assumption.

With this setup, XLB config and kernel config, I do no longer have any
PATA crashes, I do no longer have any FEC RFIFO errors, and my SCLPC
driver runs w/o problems, too.

I would be interested in your opinion, maybe Wolfgang could make some
comments, because he is involved in the U-Boot a lot as well.

Here is the original text from the Freescale support person:

-- snippety snip --

Dear Roman Fietze, 

In reply to your message regarding Service Request SR 1-597437219:

Disable pipelining also. Test your software using the following
setting of the XLB arbiter: 0x80012006.

We have request from a customer with similar problem. Problem
disappeared if XLB pipelining and BestComm snooping were disabled.

Should you need to contact us with regard to this message, please see
the notes below.

Best Regards, 

Technical Support
Freescale Semiconductor

-- snappety snap --


Roman Fietze                Telemotive AG Büro Mühlhausen
Breitwiesen                              73347 Mühlhausen
Tel.: +49(0)7335/18493-45

More information about the Linuxppc-dev mailing list