[PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards

[Hu Mingkai-B21284]

> -----Original Message-----
> From: 
> linuxppc-dev-bounces+b21284=freescale.com at lists.ozlabs.org 
> [mailto:linuxppc-dev-bounces+b21284=freescale.com at lists.ozlabs
> .org] On Behalf Of Anton Vorontsov
> Sent: Wednesday, August 19, 2009 9:51 AM
> To: Kumar Gala
> Cc: Ben Dooks; linux-kernel at vger.kernel.org; 
> sdhci-devel at lists.ossman.eu; linuxppc-dev at ozlabs.org; Andrew 
> Morton; Pierre Ossman; David Vrabel
> Subject: Re: [PATCH v2] powerpc/85xx: Add eSDHC support for 
> MPC8536DS boards
> 
> On Tue, Aug 18, 2009 at 08:24:17PM -0500, Kumar Gala wrote:
> > 
> > On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote:
> > 
> > >This patch simply adds sdhci node to the device tree.
> > >
> > >We specify clock-frequency manually, so that eSDHC will 
> work without 
> > >upgrading U-Boot. Though, that'll only work for default setup (1500
> > >MHz) on new board revisions. For non-default setups, it's 
> recommended 
> > >to upgrade U-Boot, since it will fixup clock-frequency 
> automatically.
> > >
> > >Signed-off-by: Anton Vorontsov <avorontsov at ru.mvista.com>
> > 
> > out of interest the 85xx eSDHC don't need the sdhci,wp-inverted 
> > property?
> 
> Yes, eSDHC controllers in MPC85xx report normal state in its 
> registers.
> 

Hi Anton,

The eSDHC controller in different silicon version on MPC8536  reports
different WP state in the register PRSSTAT:

Silicon 1.0:

Card WP pos    PRSSTAT[WPSPL]    RMMCR[SDHC_WP]    GENCFG[SDHC_WP_INV]
------------------------------------------------------------------------
---------------------------------------------
unLock               1                                   1
/
Lock                    0                                   1
/

Silicon 1.1:

Card WP pos    PRSSTAT[WPSPL]    RMMCR[SDHC_WP]    GENCFG[SDHC_WP_INV]
------------------------------------------------------------------------
---------------------------------------------
unLock               0                                   1
0
Lock                    1                                   1
0

Note: the register GENCFG is added on silicon 1.1 to invert the WP
state.

For silicon 1.0,  the macro SDHCI_QUIRK_INVERTED_WRITE_PROTECT is also
defined,
so the dirver will report the error WP state in function sdhci_get_ro.

Best regards,
Mingkai