[PATCH v2] powerpc: Allow perf_counters to access user memory at interrupt time
benh at kernel.crashing.org
Tue Aug 11 16:44:53 EST 2009
On Thu, 2009-08-06 at 14:57 +1000, Paul Mackerras wrote:
> This provides a mechanism to allow the perf_counters code to access
> user memory in a PMU interrupt routine. Such an access can cause
> various kinds of interrupt: SLB miss, MMU hash table miss, segment
> table miss, or TLB miss, depending on the processor. This commit
> only deals with the classic/server processors that use an MMU hash
> table, not processors that have software-loaded TLBs.
> Signed-off-by: Paul Mackerras <paulus at samba.org>
Acked-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
As discussed in the lab, you should also do a pre-req patch to pgtable.h
that changes ppc32 with 64-bit PTE without CONFIG_SMP to use the same
path as SMP to order the stores to the two halves of the PTEs though.
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