kexec on e300 core / mpc5121

[Sebastian Andrzej Siewior]

I've tried kexec on e300 core which should be easy since it is possible
to disable the MMU on that core. However it does not work.
Once I disable the MMU, I can't access my MBAR and print chars on the
serial port. Is this "normal" or do I have still some caches on?
After I've setup two BATs one for SDRAM and the other for MBAR and
enabled the MMU again, I could trace it and see that it jumped into the
new kernel. I got lost after the turn off mmu part. So the new kernel
does not boot but it gets there.

I noticed that if I boot from u-boot, my I & Dcache are switched off and
in kexec mode there are on. So I tried to disable them in my kernel
wrapper with the following sequence which I borrowed from u-boot:

|icache_disable:
|        mfspr   r3, HID0
|        lis     r4, 0
|        ori     r4, r4, HID0_ICE|HID0_ILOCK
|        andc    r3, r3, r4
|        ori     r4, r3, HID0_ICFI
|        isync
|        mtspr   HID0, r4     /* sets invalidate, clears enable and lock*/
|        isync
|        mtspr   HID0, r3        /* clears invalidate */
|        blr
|dcache_disable:
|        mfspr   r3, HID0
|        lis     r4, 0
|        ori     r4, r4, HID0_DCE|HID0_DLOCK
|        andc    r3, r3, r4
|        ori     r4, r3, HID0_DCI
|        sync
|        mtspr   HID0, r4        /* sets invalidate, clears enable and lock */
|        sync
|        mtspr   HID0, r3        /* clears invalidate */
|        blr

First icache, followed by dcache.
This has the side effect that my LR which was saved on stack suddenly
become 0x0 in the function where I disable the caches.
So it looks like the sequence above is not correct and it is probably a
cache thing why the kernel does not boot.

So I tried not to enable I & Dcache in first place. The kernel booted
uncached and then I tried to kexec into my kernel. This did not succeed,
I saw my last char printed in kernel code but nothing more. So it looks
like the same result like the cached attempt.

The HID0 register differs only in powermanagement, MSR differs in IR,DR
and PR. Is there another register which could be different? There should
be one, since I can't write anything on my serial line unless I setup
BATs and enable data address translation.
Does someone have an idea?

Sebastian